This invention relates to the field of charged particle beam lithography systems, and more particularly to a reregistration system for a parallel charged particle beam exposure system.
As integrated circuits become more complex there is a general trend in the semiconductor industry toward increasing device packaging density. The present philosophy is to keep chip or die sizes as small as possible, and so increase device yield. However, it is obvious that chip size cannot be arbitrarily reduced because of the inherent resolution limits of presently used photolithographic processes. In particular, the wavelength of light imposes a barrier to the reproduction of detail in the region of one micrometer (.mu.m).
A number of solutions have been proposed to solve the resolution problem and there is considerable activity in this area presently underway in the semiconductor industry. These solutions are based on lithographic techniques that employ particles of shorter wavelengths than visible light to overcome the resolution limitation. Generally, two classes of short wavelength particles have been proposed as alternatives to light, i.e., high energy photons (X-rays) and electrons.
An optimal lithographic system would have to possess certain attributes in order for it to be a serious contender for use in the production of integrated circuits. These attributes include resolution, coverage, lithographic speed, reregistration capability, and stability.
At present, minimum reproducible line widths on the order of 1 .mu.m are in use, and future integrated circuit structures will probably push the desired system resolution requirements to below 1/4 .mu.m. The exposure subsystem should be capable of covering the standard 75 mm and/or 100 mm wafers presently used in industry and be expandable to cover the larger (125 mm and 150 mm) sized wafers being contemplated. Clearly wafer exposure times measured in tens of minutes to hours are not acceptable in production exposure systems. Acceptable throughput conditions demand full 75 mm and/or 100 mm wafer exposure times of at most a few minutes.
A parallel charged particle beam exposure system is described in a commonly assigned copending application of Eugene R. Westerberg and Ivor Brodie, Ser. No. 227,620 filed Jan. 23, 1981, the disclosure of which is incorporated herein by reference. In this sytem, the throughput capability of conventional types of lithography systems is increased significantly by utilizing a parallel charged particle beam exposure system for directly writing an integrated circuit pattern simultaneously at a plurality of locations on a target surface.
The multilayer structure of integrated circuits necessitates that there be reregistration mechanism built into the exposure system. In general, reregistration capabilities should be a minimum of a factor of five times better than the size of the smallest detail required.
Moreover, the requirement for a very uniform electric field in the screen lens-wafer space inherent in the type of system disclosed in the aforementioned application of Westerberg and Brodie affects the reregistration process. More specifically, since the full wafer area is being written on simultaneously (rather than a chip or restricted area at a time) any signal detectors must be placed near the edge of the wafer area to avoid interference with the writing beams, and distortion of the uniform field. Likewise, since the electric field must be very uniform over the entire wafer area, the uniform field must be maintained for a significant distance beyond the edge of the wafer, to avoid edge effects.
The reregistration techniques utilized with known charged particle beam exposure systems operate in an essentially field free region, and therefore can attract, accelerate and use emitted low-energy secondary electrons for reregistration position sensing. In the aforementioned application of Westerberg and Brodie a high voltage is applied between the screen lens and wafer to provide a very uniform accelerating (and focusing) field for the multiplicity of beamlets produced by the screen lens. Accordingly, this precludes the practical utilization of low energy secondaries as taught in the prior art. For example, U.S. Pat. No. 3,875,414 issued to Prior shows the use of a fiducial mark for each field-of-accurate-deflection; e.g., 100 .mu.m.times.100 .mu.m. They are composed of very thin metal bars applied on top of the resist. A very low beam electron charge density is used to address the mark for registration, e.g., about 1% of the required writing charge density, to avoid exposing the underlying resist prior to the writing of the pattern in the field-of-accurate-deflection, including the area under the fiducial marks. This limits the scanning current during the reregistration process, which can limit the quality of the signal to be detected. In addition, the time required to reregister on each subfield reduces the time available for pattern writing and hence the throughput of the equipment.
Similarly, U.S. Pat. No. 3,900,736 issued to Michail et al., calls for reregistration at all four corners of each writing scan field to precisely define its position relative to the desired position, in order to provide corrections during the writing process for each scan field.
In addition, the utilization of a multiplicity of beamlets to directly write an integrated circuit pattern simultaneously at a corresponding plurality of locations on a target surface imposes stringent tolerance and performance requirements on the reregistration system. In particular, since the reregistration procedure is performed only once per full wafer exposure, not for each chip or die or subfield of same (at or near each individual chip location) any serious error in reregistration could cause misalignment and thus rejection of the entire wafer. Additionally, global (once per wafer exposure) registration can accommodate homogeneous changes in the wafer, such as might occur from high-temperature processing, or changes in the wafer ambient temperature between successive exposures, but cannot correct for local random movement of the prior exposed pattern on the wafer surface which, if accompanied by similar movement of the adjacent fiducial marks, could be at least partially corrected during a chip-by-chip reregistration process. However, using only a few (e.g., 2 to 4) reregistration fiducial marks in lieu of 1 or more per chip (i.e., a hundred or more for a 100 mm wafer) justifies use of more precision in fabrication of suitable fiducial marks. In addition, since time is of the essence in wafer production, reregistration only once per wafer exposure, instead of on the order of 100 times for the chip-by-chip procedure, permits more time to be invested in the global registration, to achieve improved position information by using advanced signal processing techniques and/or longer signal averaging times. Likewise, since the fiducial marks are near the edge of the wafer, they can be interrogated by the reregistration beamlets without disturbing the normal writing area of the wafer. Additionally, with multiple beam writing, the total wafer writing time can be on the order of 10 seconds, hence long term electrical or thermal drifts will have only minimal effect on the pattern writing accuracy.
It is accordingly a general object of the present invention to overcome the aforementioned limitations and drawbacks associated with the known systems and to fulfill the needs mentioned by providing a reregistration system for a charged particle beam exposure system having all of the desirable attributes noted above.
It is a particular object of the invention to provide a high resolution reregistration system for a charged particle beam exposure system.
Other objects will be apparent in the following detailed description and the practice of the invention.